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10033
Velocity Control Cycle Mismatch
Fanuc · Alpha i Series Servo Amplifier
¿Qué significa 10033 ?
This invalid parameter setting alarm occurs when the ITP (Interpolation Time Period) cycle is 16 ms, but an incorrect 500 μs is selected as the velocity control cycle. For this ITP cycle, the velocity control cycle must be 2 ms.
Causas comunes
- The sampling cycles for velocity control are not synchronized.
- Discrepancy in the timing of feedback loops within the velocity control system.
- A communication delay is causing the control loop cycle to mismatch.
- Parameter P510.1 (Control Cycle Time) is misconfigured.
Pasos de reparación & Lista de verificación
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- 1
Correct the parameter related to interrupt cycle setting to ensure the velocity control cycle is 2 ms when the ITP cycle is 16 ms.
Datos técnicos verificados. Última actualización: March 2026
Fallas relacionadas
Fuente: Fanuc Alpha i Series Servo Amplifier